3.0 Equalizer Architecture Parallel Filter Architecture 2.0 System Description a 50 Mhz 70 Mw 8-tap Adaptive Equalizer/viterbi Sequence Detector in 1.2 Μm Cmos

The multiplier is the building block required in the adaptive equalizer that is most costly in terms of both speed and power. Since the power consumed by a CMOS digital circuit is CV 2 f, reducing the power supply and employing one or a combination of parallelism and pipelining can result in a significant power savings [4]. Applications using a power supply of 3.3 V are becoming widespread in order to reap this reduction in power. Implementation of PRML channels are typically using 6 bits into the adaptive equalizer dictated by the off-channel signal-to-noise ratio. Extensive simulations were performed to explore various permutations of parallelism and pipelining in the implementation of a conventional multiplier [5] for filter sampling rates above 50 MHz and a power supply of 3.3 V. It was found that for implementation of a 6-bit by 6-bit multiplier, the use of 4 multipliers operating in parallel and staggered in phase by the output period T as shown in Figure 2 resulted in the solution dissipating the lowest overall power. This advantage of low power comes at the cost of increased silicon area which, however, will scale with technology. For the required resolution of 6 bits, the overhead associated with pipeline latches in a pipelined implementation of the multiplier increases the power while decreasing the attainable speed (due to latch setup times). A block diagram of a filter stage used to implement the FIR filter is shown in Figure 3a comprised of a delay line, a set of multipliers, and an accumulator. The filter stage resembles the block diagram of an FIR filter. In order to use multipliers which take 4 output periods to perform multiplication, 4 filter stages are used in parallel. The multiplier and accumulator sections are each clocked at one-fourth the output rate of the filter and operate staggered in phase by one output period. The parallel architecture and timing diagrams for this approach are shown in Figures 3b and 3c, respectively. The use of input latches in both the multipli-Adaptive Equalizer Viterbi Detector Data ADC Magnetic Disk Drive Read Amplifier Variable Amplifier Gain Lowpass Filter Timing Recovery Digital Processing Figure 1 Block diagram of a PR-IV magnetic disk read channel. 1 T Time A B Y 4 T Multiplier 1 Multiplier 2 Multiplier 3 Multiplier 4 Figure 2 Four multipliers operating staggered in phase by the output period T to realize an increased multiplying …